The present invention relates to the field of Cascode Radio Frequency Power Amplifiers.
In the art of radio frequency (RF) power amplifiers (PA) cascode stages are used to suppress Miller capacitance and improve the gain and frequency response of analog circuits. They provide high gain and efficiency over a broad range of input power conditions. These amplifiers are often used in transceiver systems where high power output is required. In such transceivers, the cascode stages often contain multiple transistors connected in parallel to provide high power amplification.
In an bipolar implementation of a cascode RF PA for a transceiver, the transistors of a first stage are connected in a common-emitter (CE) configuration and the transistors of a second stage are connected in a common-base (CB) configuration. Such systems are described in U.S. Pat. No. 5,274,342 to Wen. In that patent, multiple parallel transistors are provided in each stage and the output of each CE stage transistor is connected to only the input of a respective transistor of the CB stage. Thus, each pair of CE and CB connected transistors act as a separate amplifier in parallel with other separate amplifiers to reduce in-phase signal delay mismatch and prevent thermal runaway if one of the transistors heats up more than the other transistors.
Those skilled in the art are directed to xe2x80x9cA Novel MMIC Power Amplifier for Pocket-Size Cellular Telephonesxe2x80x9d by Masahiro Muraguchi et. al., IEEE MTT-S, 793-796, 1993.
The above citations are hereby incorporated in whole by reference.
In the invention herein, an CMOS integrated circuit chip has a cascode RF PA with a first cascode stage of one or more first transistors connected in parallel, and a second stage of one or more second transistors connected in parallel. The inputs of the second stage transistors are connected in series to the outputs of the respective first stage transistors. The inputs of the first stage transistors are connected to ground and the outputs of the second stage transistors are connected to a reference voltage through an impedance. An RF input signal is provided to the gates of the first stage transistors and a signal output is provided from the output of the second transistors. A bias voltage is connected through an impedance to the gates of the second transistors. The use of two stages reduces the peak voltage between the gates and the inputs and outputs of the respective transistors so that gate oxide is not ruptured.
In a MOSFET implementation, the connection configuration described above for the first transistor, is referred to as common gate configuration and thus the first stage is referred to as the common gate stage. Similarly for MOSFET circuits the connection configuration described above for the second transistor, is referred to as common source configuration and thus, the second stage of the PA is called the common source stage.
The gates of the second transistors are connected to ground through a series combination of a small on-chip capacitor and an off-chip inductance to provides a well controlled resonant short circuit at the operating frequency. This termination cancels the impedance at the gate so as to suppress the occurrence of negative resistance at the gates of the second transistors by eliminating the feedback from the output of the second transistors to the gates of the second transistors. This also provides a compact implementation with minimal parasitic effects and unwanted oscillations.
In a wirebond implementation, the off-chip inductances may be provided by bond wires connected to bond pads connected to the on-chip capacitors. In a flip chip implementation, the inductances may be provided by inductive traces of the circuit board or by external wire coils connected through a flip-chip joint to the on-chip capacitors. Preferably, the size and/or number of on-chip capacitors and corresponding off-chip inductances are selected to provide a well controlled resonant short circuit at the first harmonic of the operating frequency to further suppress negative resistance of the CG stage.
Preferably, the transistors are metal-on-silicon field-effect transistors (MOSFETs), and more preferably NMOS transistors. The use of a two stage amplifier prevents gate rupture in deep submicron CMOS ICs (e.g. for 0.25 micron CMOS technology, gate rupture will occur at 6V, which can easily be exceeded between the gate and drain terminals in a PA, during RF operation, with a supply voltage as low as 2.5V). The invention allows the use of a pure CMOS design thereby minimizing the cost of the transceiver. Also, preferably, an on-chip resistance is provided for the bias input of the gate of the CG stage to limit the current to the gate.
Those skilled in the art will understand the invention and additional objects and advantages of the invention by studying the description of preferred embodiments below with reference to the following drawings which illustrate the features of the appended claims: